The present invention generally relates to a semiconductor device and, more particularly, to a technique which can be effectively applied to a field effect transistor for power amplification of high frequency band, e.g., UHF band.
Conventionally, an electronic device module for high frequency amplification (which module will be referred to merely as the module, hereinafter) is known as an electronic device. This sort of module will be briefly explained by referring to FIG. 1.
FIG. 1 shows, in plan view, a Prior Art high frequency amplification module already assembled but not coated or sealed with resin. In the drawing, high frequency current is input and output to field effect transistor (FET) chips 14a, 14b and 14c through a high-frequency power matching circuit which comprises a plurality of conductive strip lines 18 and capacitors 21 (C1 to C13). More specifically, high frequency power is supplied from an input lead 22d through the matching circuit to the respective FET chips 14a, 14b and 14c, where the power is amplified and then externally output from an output lead 22a via the matching circuit.
Printed resistors 20 include bleeder resistors for obtaining a predetermined bias voltage, high-frequency current blocking resistors and voltage supply resistors to the respective FETs. These printed resistors 20 are shown in the form of hatched rectangles. An automatic power control (APC) lead 22c is a terminal for control of output power while a power supply lead 22b is a terminal for power supply. 0 V or a positive DC voltage is applied to lead 22c, while a positive DC voltage is applied to the lead 22b. A header 11, which corresponds to a minus terminal of a DC power source, functions as a heat radiating plate and as a grounding (GND) terminal. The header 11 also acts as a flange for fixed mounting of the module.
The module of FIG. 1 further includes a ceramic substrate 4, through holes 12a, 12b and 12c made in the ceramic substrate, heat sinks 13a, 13b and 13c, post tabs 15a, 15b and 15c, aluminum bonding wires 16a, 16b and 16c, and GND lines 19 which are electrically connected to the rear surface (which is metallized) of the ceramic substrate 4 by the through-hole printing.
For a better understanding of the present invention, explanation will be made as to the FET chip 14a as the output stage of the module of FIG. 1 and a peripheral part thereof, with reference to FIG. 2 showing its cross-sectional view. The header or support plate 11 is made of a copper plate coated at its both surfaces with nickel (Ni). Placed on one surface of the header 11 is the ceramic substrate 4 on which a wiring pattern of Cu strip line conductors 18 and the rear surface (facing the header 11) of which is solid printed with Cu. Solder 3 interconnects the rear surface of the ceramic substrate 4 and the front surface of the header 11. Further soldered by means of the solder 3 onto the front surface of the header 11 with Au-Si eutectic is the Cu-made heat sink 13a to which the Si-FET chip 14a is previously die-bonded. In the illustrated example, the front surface of the heat sink 13a the is plated with Au material and which rear surface is plated with Ag material, allowing easy die-bonding and soldering in the form of eutectic.
The post tabs 15a are bonded by solder 3' to one ends of the strip line conductors 18 on the front surface of the ceramic substrate 4. In the illustrated example, since each post tab 15a is made of a Fe-Ni alloy body plated on its front surface with aluminum cladding material and on its rear surface with solder, the post tab allows utilization of ultrasonic bonding of its front surface by means of Al wire and also a good soldering of its rear surface.
The FET chip 14a is wired to the respective post tabs 15a through the aluminum wires 16a by ultrasonic bonding. In FIG. 2, the left-side tab is used as a gate and the right-side tab is used as a drain. In the illustrated FET chip 14a, since heat sink is connected to a source, the heat sink 13a itself becomes a source electrode. Since the heat sink 13a is made of Cu material, the heat sink is electrically connected to the header 11 at the GND potential with a very low source resistance.
In this way, the FET chip 14a is mounted on the header 11 in its bare state and the FET chip 14a and the ceramic substrate 4 are interconnected by means of wire bonding. Such a structure will be referred to as bare chip mounting, hereinafter.
The above module is subjected in a sealing step to a moisture-proof coating with use of phenolic resin and silicone resin and then attached with a resin cap, thus completing a finished product.
The above explanation has been made in connection with an example where the Si-FET bare chips are mounted on the substrate and the header on the bare chip mounting basis. However, when it is desired to mount GaAs-FET chips, a chip carrier package mounting system, which will be explained below, is employed.
An example of an Si bipolar transistor chip carrier is shown in FIGS. 3A and 3B. More specifically, FIG. 3B is a cross-sectional view of the chip carrier taken along line III B--III B in FIG. 3A. Since a bipolar transistor usually has an Si substrate as its collector and is grounded at its emitter, it is necessary to electrically separate or isolated the collector from the ground GND. In addition, since the collector requires much heat radiation, it is necessary to couple the collector to a material having a good thermal conductivity.
To meet such requirements, a chip carrier including a heat sink of beryllia as shown by a plan view in FIG. 3A and by a cross section in FIG. 3B is used. Since beryllia is insulating material and excellent in thermal conductivity, it has been long employed in such applications.
The chip carrier of FIGS. 3A and 3B includes a beryllia material 30, a printed base electrode 31, a printed collector electrode 32, a printed grounding (emitter) electrode 33, a base lead 34, a collector lead 35, an emitter tab 36, an Au-Si eutectic material 37, an Si-bipolar transistor chip, 38 and Au wires 39.
Shown in FIGS. 4A and 4B is an exemplary GaAs-FET chip carrier. More specifically, FIG. 4B is a cross sectional view of the chip carrier taken along line IV B--IV B in FIG. 4A. Since the substrate of a GaAs FET is made of semi-insulating material, a source bonding pad is connected in series by means of bonding wires 51 as shown by a plan view in FIG. 4A and also electrically connected to a heat sink 42. The heat sink 42 is made of Cu or the like metallic material for the purpose of attain a source grounding as shown by the cross section in FIG. 4B. Electrical isolation between the heat sink 42 and a gate lead 48 or a drain lead 47 is established by means of an electrically substrate 41. A GaAs chip substrate 50, which is unsuitable in eutectic die-bonding, is die-bonded by means of low-temperature Au-Ge brazing material 49.
The chip carrier of FIGS. 4A and 4B further includes a printed gate electrode 43, a printed drain electrode 44, a printed source electrode 45, source leads 46, and the Au wires 51.
In the foregoing, explanation has been made in the connection with the ceramic chip carriers for both Si bipolar transistor and GaAs FET. Both ceramic chip carriers are plated with Au material to provide an improved bonding property.
A package of an Si insulated gate FET for high frequency power amplification is known as shown in FIGS. 5A and 5B (for example, refer to JP-A-57-178370 laid open on Nov. 2, 1982). In more detail, FIG. 5B is a cross section of the package taken along line V B--V B in FIG. 5A. However, a heat sink 61 is structurally designed so as to be fixed to a heat radiating plate or a printed circuit board by screwing means. For this reason, the heat sink is suitably mounted onto a flat substrate without any through holes. Mounting of the heat sink to the ceramic substrate of such a module 1 as shown in FIG. 1 is disadvantageous in many respects including a space inefficiency because the heat sink must be inserted into a through hole in the ceramic substrate and then connected to the header by soldering. The package of FIGS. 5A and 5B includes a header 62, a chip 63, leads 64, 65 and 66, a source electrode 67, wires 68, a gate electrode 69, a drain electrode 70, and a resin coat 71.
Explanation will next be made as to mounting of a chip provided with a ceramic chip carrier. Referring to FIG. 6, there is shown, in cross section, a state in which an Si bipolar transistor provided with such a ceramic chip carrier as shown in FIGS. 3A and 3B is fabricated into a module. As shown in FIG. 6, the ceramic chip carrier for the Si bipolar translator is connected by the solder 3 to the ceramic substrate 4 and the header 11 and then subjected to a moisture-proof coating with use of silicone resin 52, thus completing a module as a finished produce.
FIG. 7 is a cross-sectional structure of a module into which a GaAs FET package comprising such a ceramic chip carrier as shown in FIGS. 4A and 4B is fabricated. As shown in FIG. 7, the GaAs FET ceramic chip carrier is connected by the solder 3 to the ceramic substrate 4 and the header 11 and then subjected to a moisture-proof coating with use of the silicone resin 52, thus completing a module as a finished product. FIG. 7 shows a state (an area encircled by a circle A in FIG. 7) where the solder 3 has risen up the Au plated side surface of the heat sink of the chip carrier, which can occur during the soldering of the chip carrier to the header 11. Since the Au plated surface has a very good soldering property, the Au plated surface tends to adhere excessive solder which can cause a short-circuit (in the illustrated example, short-circuiting between the gate and source) due to the solder excessively filling the void formed therein.
In the Example of FIG. 6, while the ceramic chip carrier is illustrated without the excessive solder filling the void, thus avoiding a short circuit, a similar trouble as in the above example of FIG. 7 may take place because the surfaces (front and back surfaces relative to FIG. 6) of the heat sink 30 are plated with Au material. Excessive solder can fill the void created therein and cause a short between the emitter (ground) and collector or base and emitter.
Techniques associated with the fabrication of a power MOS FET for high-frequency power amplification are disclosed, for example, in JP-B-45-11775 (published after post-examination on Apr. 28, 1970), JP-B-49-6514 (published after post-examination on Oct. 1, 1974), JP-A-53-68581 (laid open on Jun. 19, 1978) and JP-A-58-137256 (laid open on Aug. 15, 1983).